This invention relates to data processors and, more particularly, to a processing system incorporating a set of modules which are activated by a common data bus, but perform processing operations on sequential blocks of the data in staggered time sequence.
Data processors, such as computers, are often used in situations wherein additional processing power is desirable. Indeed, systems employing data processors can be more readily adapted to perform a task when higher throughput rates are available. Furthermore, when such systems are used in avionics, the systems have the added requirements of modularity, expandibility, adaptability for incorporating new technologies, and fault tolerance.
Processing systems may incorporate many microprocessors to perform arithmetic operations, data sorting, and other processes with the incoming data. Fortunately, microprocessors are becoming one of the least expensive components of a computer system. Typically, more engineering effort is expended on software design, debugging, and modification than is expended on the corresponding hardware tasks. Therefore, it is most desirable to have a computer system which can be upgraded to incorporate future developments in technology without necessitating a complete rewrite of the software.
However, a problem exists in that with present data processing equipment, the computer hardware and software are so interrelated that a change in hardware configuration usually results in a need for extensive software revision. The computer architecture does not permit the replacement of one type of processing component with another type of processing component without a corresponding rewrite of the software. Thus, a processing component of a data processor cannot readily be updated to incorporate recent technological developments.
A further problem encountered in data processing equipment is the difficulty in increasing the data throughput rate. One method of improving the throughput rate of a process is to increase the computational efficiency of an algorithm as is done in the computation of a fast Fourier transform of a set of numbers. Algorithms are also used for the efficient machines solution of a large class of general problems such as sorting, numerical approximations, and matrix operations. In the design of data processing equipment and in the development of the algorithms to be used therewith, a tradeoff is often made between program or data memory requirements and execution time. Such a tradeoff is exemplified in the choice of calculating trigonometric functions using the Taylor expansion, or by using a lookup table. Also, the instruction set of a computer can have such impact on program efficiency as may be seen, by way of example, in the microcoding of the instructions for the evaluation of a polynomial.
Another atempt at the increasing of the throughput rate is the use of a set of processors operating in a pipeline format. Therein, a series of functional modules are interconnected by registers to allow partially completed terms of a mathematical process to propagate down the pipeline for completion in the latter modules. Thereby, the modules can operate simultaneously. Such an interconnection of the hardware is useful when the same operation is performed repeatedly on different data. For example, a multiplier may be pipelined by reducing it to a series of adders and inserting registers between the adders. For a pipelined system, the fundamental operation must be determined before the hardware is designed. Pipelining is limited in its adaptability in that recursive functions cannot be speeded up by simply inserting registers, since a new calculation cannot begin until previous calculations by a previous module has been completed.
Another arrangement of data processing elements which is used to increase the throughput rate is the array processor. An array processor is a computer with a multiplicity of arithmetic logic units and a single program control structure. Array processors are usually difficult to program efficiently, since the function to be implemented by the processor must be made to fit the array size. Programs written in a higher level language for a sequential machine cannot be compiled in an array processor to make full use of the parallel architecture.
Even with multiprocessors, difficulties are still experienced in maximizing a throughput rate. A multiprocessor is a system containing more than one processor, each with its own arithmetic logic unit and control structure. Processors may share memory for interprocess communication or economy. Multiprocessors often are subject to the same consideration that pertain to pipeline architecture. Unless the required function to be performed inherently has a high degree of separate, noninteracting operations, the function must be separated into sequential calculations which are then performed in the various processors of the system. In general, all processors run different programs and the entire system is required to debug the software. The timing of interprocess interaction makes this software unduly complicated.